1. Field of the Invention
The present invention relates to a non-volatile memory device. More particularly, the present invention relates to a flash memory cell and manufacturing method thereof.
2. Description of the Related Art
Flash memory is a device that allows multiple data writing, reading and erasing operations. In addition, the stored data will be retained even after power to the device is removed. With these advantages, flash memory has been broadly applied in personal computer and electronic equipment.
A typical flash memory device has a floating gate and a control gate fabricated using doped polysilicon. The control gate is set up above the floating gate with an inter-gate dielectric layer separating the two. Furthermore, a tunneling oxide layer is also set up between the floating gate and an underlying substrate to form a so-called stacked gate flash memory cell.
FIG. 1 is a schematic cross-sectional view showing the structure of a conventional stacked gate flash memory cell (according to U.S. Pat. No. 6,214,668). As shown in FIG. 1, the flash memory includes of a p-type substrate 100, a deep n-well region 102, a p-type pocket doped region 104, a stacked gate structure 106, a source region 108, a drain region 110, spacers 112, an inter-layer dielectric layer 114, a contact plug 116 and a conductive line 118 (a bit line). The stacked gate structure 106 further includes a tunneling oxide layer 120, a floating gate 122, an inter-gate dielectric layer 124, a control gate 126 and a cap layer 128. The deep n-well region 102 is located within the substrate 100 and the stacked gate structure 106 is located above the p-type substrate 100. The source region 108 and the drain region 110 are located within the p-type substrate on each side of the stacked gate structure 106. The spacers 112 are attached to the sidewalls of the stacked gate structure 106. The p-type pocked doped region 104 is located within the deep n-well region 102 and extends from the drain region 110 to the area underneath the stacked gate structure 106. The inter-layer dielectric layer 114 is set above the p-type substrate 100. The contact plug 116 passes through the inter-layer dielectric layer 114 and the p-type substrate 100 and shorts the drain region 110 and the p-type pocket doped region 104 together. The conductive line 118 is positioned over the inter-layer dielectric layer 114 but is electrically connected to the contact plug 116.
In the aforementioned flash memory cell, the conductive line 118 (the bit line) connects through the contact plug 116 with the drain region 110 and the p-type pocked doped region 104 each having a different electrical conductive state. In general, the contact of the drain region 110 and the p-type pocked doped region 104 with the contact plug 116 is usually poor (a small contact area between the contact plug 116 and the drain region 110 due to vertical contact). Therefore, the electrical resistance near the drain region and the p-type pocket doped region 104 is unusually high or unstable when the memory cell is carrying out an operation (especially when the memory cell is carrying out a reading operation). An increase in electrical resistance often slows down device operation and leads to a drop in overall performance.
In addition, in the step of forming the contact plug 116, the inter-layer dielectric layer 114 and the p-type substrate 100 have to be etched so that a contact hole penetrating the inter-layer dielectric layer 114 and the drain region 110 is formed. Since the contact hole has a relatively high aspect ratio and two different types of materials (silicon oxide and silicon) need to be etched in the etching process, controlling the depth of the contact hole is very difficult. Furthermore, in a later stage processing operation, the contact plugs in the memory cell region and the contact plugs in the peripheral circuit region have to be formed separately. In other words, subsequent fabrication process is also quite complicated.